1. Field of the Invention
The present invention relates to an SRAM (Static Random Access Memory) device including a redundant memory block (spare memory block).
2. Description of the Related Art
An SRAM device of a split word line type includes split word lines, such that only a number of memory cells (normal memory cells) are coupled to selected ones of the split word lines, where the number corresponds to a number N of bits in the I/O (input/output), thereby avoiding charging/discharging of bit lines associated with any unaccessed memory cells for the sake of power economy.
In large-capacity SRAM devices, it is essential to provide redundant memory cells (spare memory cells) for achieving a high production yield. Also, in SRAM devices which are produced by processes which are susceptible to a large defect density, it is essential to provide redundant memory cells (spare memory cells) for an improved production yield. This is the reason why redundant memory cells are incorporated in such SRAM devices.
Redundant memory cells need to be selected and activated simultaneously with normal memory cells. In the case where redundant memory cells are provided in an SRAM device of a split word line type, it is necessary to additionally provide and couple M redundant memory cells to each of the split word lines (where M is a natural number). Therefore, conventionally, a total of (N+M) memory cells, i.e., N normal memory cells and M redundant memory cells, are coupled to one split word line. It is also necessary to provide a selection circuit (coupling circuit) which, for each split memory block that corresponds to each split word line, selects N data lines from among the data lines corresponding to (N+M) bits. Such a selection circuit, which is typically implemented by employing non-volatile programming elements such as fuses, occupies a large area. This leads to a problem in that, when redundant memory cells are provided in an SRAM device of a split word line type, the overall area occupied by the SRAM device becomes large. A larger area being occupied by an SRAM device leads to a greater area penalty incurred by that SRAM device. As used herein, an xe2x80x9carea penaltyxe2x80x9d for an SRAM device means an increased probability for the SRAM device to contain defects due to an increased area occupied by the SRAM device.
An SRAM device according to the present invention includes: a plurality of normal memory blocks each including N normal memory cells for storing data, wherein N is a natural number; a spare memory block including one or more spare memory cells for storing data; a defective block setting section for storing first defective block information indicating a normal memory block including a defective normal memory cell among the plurality of normal memory blocks; N internal data lines which are respectively coupled to the N normal memory cells included in each of the plurality of normal memory blocks, where the N internal data lines are used for reading data stored in the N normal memory cells included in one of the plurality of normal memory blocks which is designated by access information, wherein the access information is externally input to the SRAM device; one or more spare data lines coupled to the spare memory block for reading data from the one or more spare memory cells included in the spare memory block; N external data lines via which the SRAM device outputs the data; and a coupling circuit for, depending on whether or not the first defective block information matches the access information, either coupling those of the N internal data lines which are not coupled to a defective normal memory cell in the normal memory block indicated by the first defective block information and at least one of the one or more spare data lines to the N external data lines, or coupling the N internal data lines to the N external data lines.
In one embodiment of the invention, the defective block setting section further stores second defective block information indicating a defective normal memory cell among the N normal memory cells included in the normal memory block indicated by the first defective block information.
In another embodiment of the invention, the defective block setting section includes non-volatile programming means for storing the first defective block information and the second defective block information.
In still another embodiment of the invention, the spare memory block includes a spare word line which is coupled to at least one of the one or more spare memory cells included in the spare memory block; and the spare word line is activated independently from the access information.
In still another embodiment of the invention, the spare memory block includes a spare word line which is coupled to at least one of the one or more spare memory cells included in the spare memory block; and the spare word line is activated in accordance with the access information.
In still another embodiment of the invention, the coupling circuit couples those of the N internal data lines which are not coupled to the defective normal memory cell and the at least one of the one or more spare data lines to the N external data lines in a predetermined order.
In still another embodiment of the invention, the SRAM device further includes a main word line; each of the plurality of normal memory blocks further includes a split word line coupled to the N normal memory cells included in each of the plurality of normal memory blocks; and the split word line included in each of the plurality of normal memory blocks is coupled to the main word line.
Thus, the invention described herein makes possible the advantage of providing an SRAM device of a split word line type which incorporates redundant memory cells and which can reduce an area penalty associated therewith.
This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.